In this paper we describe an FPGA implementation of a previously proposed architecture that performs motion estimation in image coding using the full-search Block-Matching algorithm. The emphasis of this work is to evaluate the suitability of this technology to solve the motion estimation problem (one of the most demanding parts of the image coding process). The result is a two-FPGA implementation that performs at 925 MOPS.
Year:
1996
Type of Publication:
Journal publications
Journal:
6th International Workshop on Field-Programmable Logic and Applications, FPL '96 Darmstadt, Germany, September 23–25, 1996 Proceedings