Publication (Conferences and Seminars)

VLSI architecture for motion estimation using the block-matching algorithm

Sanz Álvaro, César; Garrido González, Matías; Meneses Chaus, Juan Manuel

Abstract:

In this paper an architecture is described that implements motion estimation in image coding, using a block-matching algorithm and an exhaustive search method. The architecture, EST256, consists of 256 processor elements, deals with a search area of -8/+7 and performs 11 GOPS (subtraction, absolute value determination, accumulation and comparison). It is implemented with ES2 0.7 μm double-metal-layer CMOS technology. This ASIC is cascadable to deal with bigger search areas

Year:

1996

Type of Publication:

Conferences and Seminars

Month:

March

ISBN:

0-8186-7424-5

ISSN:

1066-1409

DOI:

10.1109/EDTC.1996.494318