Publication (Conferences and Seminars)

VLSI Architecture for Motion Estimation in Image Coding using the Three-Step Block Matching Algorithm

Sanz Álvaro, César; Garrido González, Matías; Meneses Chaus, Juan Manuel
In this paper an architecture is described that implements motion estimation in image coding, using a block-matching algorithm and an exhaustive search method. The architecture, EST256, consists of 256 processor elements, deals with a search area of -8/+7 and performs 11 GOPS (subtraction, absolute value determination, accumulation and comparison). It is implemented with ES2 0.7 µm double-metal-layer CMOS technology. This ASIC is cascadable to deal with bigger search areas.
Type of Publication:
Conferences and Seminars