Publication (Conferences and Seminars)

The MVIP-2 Architecture for H.263 Video Coding

Garrido González, Matías; Sanz Álvaro, César; Jiménez, M.; Meneses Chaus, Juan Manuel
MVIP-2, a flexible and efficient architecture that implements the core of a video coder according to Rec. H.263, is presented in this paper. It consists of a RISC that controls the scheduling of a set of specialized processors for the transforms (DCT and IDCT), quantizers (DQ and IQ), motion estimation (ME) and motion compensation (MC). The architecture also includes preprocessing modules for the input video signal from the camera and interfaces for external video memory and H.263 bit-stream generation. The architecture has been written in synthesizable Verilog and tested using standard video sequences. We are now prototyping MVIP-2 on a commercial development system based on an EP20K400BC652 FPGA and an ARM7TDMI RISC.
Type of Publication:
Conferences and Seminars