Research

Publication (Conferences and Seminars)

A flexible architecture for H.263 video coding

Garrido González, Matías; Sanz Álvaro, César; Jiménez, M.; Meneses Chaus, Juan Manuel
Abstract:
In this paper a very flexible and efficient architecture that implements the core of a video coder according to Rec. H.263 is presented. It consists of a RISC processor that controls the scheduling of a set of specialized processors for the transforms (DCT and IDCT), quantizers (DQ and IQ), motion estimation and motion compensation (ME/MC). The architecture also includes preprocessing modules for the input video signal from the camera and interfaces for the external video memory and the H.263 bit-stream generation. The architecture has been written in synthesizable Verilog and tested using standard video sequences. It has also been prototyped into a development system based on an FPGA and a RISC.
Year:
2002
Type of Publication:
Conferences and Seminars
ISBN:
0-7695-1790-0
DOI:
10.1109/DSD.2002.1115353