Publication (Phd Thesis)

Contribución a las Metodologías de Optimización del Tiempo de Ejecución de Algoritmos de Descodificación de Vídeo sobre DSPs

Pescador del Oso, Fernando
This Ph. D. work is integrated in the research topics carried out by the Electronic and Microelectronic Research Group of the Universidad Politécnica de Madrid. These topics are focused on implementing video coding applications. Several theses have been developed previously in this line of activity. In these theses the research has been focused on specific hardware architectures oriented to the implementation of digital video encoders. However, the constant emergence of new video coding standards and the time required to develop specific implementations using hardware architectures, make it necessary to consider other flexible technology solutions. These solutions must also reduce the development time (time to market) of this kind of applications. The emergence of the so-called media processors that consist of a digital signal processor (DSP) and some peripherals targeted at video applications is an interesting technological alternative due to its flexibility. The design of encoders and decoders using DSPs starts with the selection of a reference software implementation, designed to run on a personal computer. This code is migrated to the DSP environment and optimized to achieve real time operation. During the last years several papers have been published focused on the optimization of video encoders and decoders using DSP technology. However, no publications were found describing a working method that take into account the complete process and help to carry out more efficiently. The main objective of this thesis is the research on a methodology to design and develop a complete system of encoding/decoding of digital television on digital signal processors. In order to provide a methodology as general as possible, it has been developed using the data obtained after implementing decoders compatible with a set of standards and using different DSPs. The experiments were performed for implementations of decoders, but the methodology can be also useful in the design of encoders, largely because similar algorithms are used. The research to achieve the proposed methodology has been carried out in four phases that are summarized below. First, a study of coding standards MPEG 2, MPEG 4 and H.264 from the point of view of the tools they use is presented. This study shows their similarities, which has facilitated the application of optimization methodologies defined to all of them. Secondly, an analysis of the state of the art in two key areas for the development of the thesis has been done: the latest generation DSPs and the optimization techniques of video encoders and decoders based on DSP. This analysis has shown that the internal architecture of all DSPs is similar. This enables that the optimization methods validated for some of them are relevant to the rest. On the other hand, a lot of papers describe optimization techniques for video encoders and decoders on DSP technology. However, as mentioned before, no publications were found describing the overall working methods. Thirdly, the implementations of MPEG-2, MPEG-4 and H.264 using TMS320DM642 and TMS320DM6437 signal processors are described. Some optimizations techniques have been used to reduce the execution time. Real time performance has been achieved for the three standard video decoders for standard definition (SD) sequences. These implementations have a better performance than that of others described in the literature. These techniques have been classified in three groups: those related to the management of code and data at different levels of internal DSP memory, those related to the data movement between internal and external memories and those who take advantage of the SIMD architecture. Each optimization technique has been documented and a summary has been created. This summary describes the technique implementation and its possible generalization to the optimization of decoders compatible with other standards or implementations with different DSPs. Fourthly, a complete digital TV reception via IP (Set Top Box IP or STB-IP), developed entirely within the framework of this thesis, is described. This STB-IP has been developed in order to perform tests with real TV broadcasts. This platform has allowed completing the optimization methodology with some recommendations that affect to complex systems. Two prototypes boards have been used to implement the STB-IP: one designed within the framework of this thesis based on the TMS320DM642 DSP and a commercial board based on the TMS320DM6437 DSP. A methodology for optimizing algorithms for encoding or decoding digital video using digital signal processors has been synthesized using the information obtained in previous experiments. This methodology is based on some recommendations to be applied sequentially to improve the performance of the encoders or decoders. Some of the optimization techniques that have been used in the thesis are described in different publications but, a general methodology that unifies the application of these techniques from the selection of the reference software to the development of a complete system has not been presented so far. The application of this methodology in future designs will substantially reduce the time needed to implement encoders or decoders based on DSPs.
Research areas:
Type of Publication:
Phd Thesis
Type of Publication:
PhD Thesis